module 	pip_reg #(parameter N = 8 ,parameter zero = 8'b0) (
    input	    		      clk,
    input	    	    	rst_n,
    input	    	    	flush,
    input                     ena,
    input	    [N-1:0]    data_i,
    output	    [N-1:0]	   data_o	
);       reg    [N-1:0]	   data_reg;
    /*initial begin
        data_reg<=zero;
    end*/   
		 
    always@(posedge clk or negedge rst_n)  begin         
            if(!rst_n)begin
                data_reg<=zero;
            end
            else if(ena) begin                
                if (flush) begin
                    data_reg<=zero;                    
                end else begin
                    data_reg<=data_i;                 
                end
            end
            else begin 
                data_reg<=data_reg;
            end                     
    end
    assign data_o = data_reg;
endmodule